Dynamic Response of Jospephson Resistive Logic (JAWS) GATE

--In this paper a thorough investigation of resistive logic gate, JAWS (Josephson Auto-Weber System) has been made. The current equations of this gate at each stage have been deduced. The dynamic response of this gate has been obtained by the computer-simulation. Our concept of turn-on delay of Josephson junction has been introduced. The effect of overdrive current on turn-on delay for JAWS resistive logic gate has been shown. This will provide a better understanding of switching dynamics of the JAWS logic gate. Further, we have shown the effect of overdrive current on this logic gate. ——————————  —————————— INTRODUCTION wo attractive features of SQUID devices for logic applications are isolation and serially connected fan-out. The isolation is provided by the transformer coupling between the SQUID and the input. The isolation is not perfect in the sense that a noise pulse (typically 5 percent) is fed back into the control line when the SQUID switches to the non-zero voltage. The other advantage is the serial fan-out capability by which the control lines of many load devices can be connected in series with a single output line. The main drawbacks of SQUID devices for logic application are relatively large device area and high sensitivity to stray magnetic fields. In SQUID 80% of the area is occupied by the transformer [1]. Further, the high sensitivity to stray magnetic field requires that the SQUID based logic circuits be well shielded from the stray magnetic fields. The resistive logic gates such as JAWS (Josephson Auto-Weber System) [2], DCI (Direct Coupled Isolation) [3] and RCJL (Resistor Coupled Josephson Logic) [4] are chosen because the gate logic delay in this case would consist of the turn-on delay, switching delay and propagation delay, but not the crossing delay as in the case of magnetically coupled logic gates. Further, these resistive logic gates do not have a factor of limiting the size very seriously. So, the gate propagation delay can be made sufficiently small. Therefore, the small time constant of the Josephson junction can be directly attained to these gates. It has been considered by the earlier workers [5] that the turn-on delay of a logic gate is the time taken for the logic gate to obtain 2% of the output current to the load. This consideration seems to be orbitrary.  DEPARTMWENT OF PHYSICS, GMR INSTITUTE OF TECHNOLOGY, RAJAM-532127,A.P., INDI,A Email : [email protected] [email protected]  DEPARTMENT OF ELECTRONICS AND ELECTRICAL COMMUNICATION ENGINEERING, INDIAN INSTITUTE OF TECHNOLOGY , KHARAGPUR-721302 INDIA. Due to this fact, in the present paper we have made a thorough investigation of the resistive logic gate JAWS. Our concept of turn-on delay[6] has been introduced which will be able to remove the confusion in critically ascertaining the switching speed of these logic gates. Further, the effect of overdrive current on these resistive logic gates has been studied. JAWS (Josephson Auto-Weber system A gate of this kind has been reported by Fulton, et al [2] and is called JAWS. The basic gate employs two junctions and a resistor as shown in Fig.1 where J1 and J2 represent Josephson junctions with critical currents 2Io and Io and junction capacitances 2Cj and Cj respectively. RL is the load resistor with a resistance rL. R is the input resistor with a resistance r The JAWS gate is biased in the superconducting state by the gate current Ig and the offset current Ioff. The current levels in J1 and J2 are Ig -Ioff and Ioff, respectively. When the input signal Iin is directly injected to this JAWS device, it will add to the bias current in junction J1 and subtract from the bias current in junction J2. The junction J1 is a current-summing junction which switches first in the gate. This makes J1 highly resistive, steering most of the signal and the gate current leads to ground through the resistor R. The gate current Ig is selected to be sufficient to then switch J2 to the non-zero voltage state. With both J1 and J2 in the high-resistance state, the gate current is steered to the load R and the signal current to ground via the resistor R. The high-resistance of J2 prevents gate current from feeding back into the input signal line and thus provides isolation. However, the isolation is not perfect and a small amount of current (typically 5%) is fed back into the input line. T International Journal of Scientific & Engineering Research Volume 2, Issue 10, Oct-2011 2 ISSN 2229-5518 IJSER © 2011 http://www.ijser.org In Fig.2 we have shown the current equations at each stage of the logic gate mentioned. According to Fig.2, the current equation at each stage can be written as: Fig. 1 Circuit configuration of the resistive logic gate JAWS with threshold characteristics. Fig. 2 Circuit configuration of the resistive logic gate JAWS with current indication at each stage of the logic gate. dt dV C I i a j a o 2 sin 2 1    (1) ) ( ) ( sin 2 b a j b a o V V dt d C I i       (2) r V i b / 3  (3) L a r V i / 4  (4) dt d V dt d V b o b a o a       2 , 2   (5) 4 2 1 i i i I g    (6) and 3 2 i i i I off in    (7) (Note: Here the effect of subgap quasiparticle resistance Rj has been neglected since Rj >>r, r, ). a) Static case: 0 0 0 4 3        i i dt d V V b b a  After using the above conditions Eqns.(1) and